Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language Third Part: Ternary Non-Combinational (Sequential) Logic Components
| dc.contributor.author | Al-Humidi, Abdullah Ali | |
| dc.contributor.author | Asaad, Abdulraqib Abdo | |
| dc.date.accessioned | 2026-06-15T23:15:47Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | In this scientific paper, the third part of the software library for the Ternary non-combinational (Sequential) logic components (the components that store information) will be built based on VHDL language starting by the Ternary D Latch (TDL) and ending by the Ternary RAM (TRAM). | en_US |
| dc.identifier | 10.20428/jst.v24i2.1641 | |
| dc.identifier.citation | Al-Humidi, A. A., & Asaad, A. A. (2020). Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language Third Part: Ternary Non-Combinational (Sequential) Logic Components. Journal of Science and Technology, 24(2), 47-75. https://doi.org/10.20428/jst.v24i2.1641 | en_US |
| dc.identifier.uri | https://repository.ust.edu.ye/handle/123456789/412 | |
| dc.identifier.uri | https://journals.ust.edu/index.php/JST/article/view/1641 | |
| dc.language.iso | en | |
| dc.publisher | University of Science and Technology, Yemen | en_US |
| dc.title | Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language Third Part: Ternary Non-Combinational (Sequential) Logic Components | en_US |
| dc.type | Article | en_US |